In recent years, ball grid array (BGA) packages for semiconductor chips have been used extensively in the semiconductor industry. BGA packages utilize solder balls for establishing electrical interconnections between a chip and a printed circuit board (PCB) and provide high quality and reliability. It has been commonly used in CPU chips in personal computers, in chips of multi-chip modules and in other high I/O chips.
A BGA package can be made more compact in size than other packages, for instance, than a plastic quad flat package (PQFP). A BGA package which has an IC chip wire bonded to a substrate can be easily soldered to a printed circuit board by solder balls which are arranged in an area array. Other benefits can also be achieved by the BGA package. For instance, there are fewer soldering defects in a BGA assembly when compared to the PQFPs and the self-alignment effect of the solder balls. As a result, minor misalignments in the mounting position can be automatically corrected by the surface tension of the molten solder during a reflow process.
The BGA package utilizes an area array external electrodes which are normally formed of lead/tin solder balls. The solder balls are placed on a back surface of the package at spacings between about 1 mm and about 1.5 mm. The BGA package further provides the benefits of higher external pin-count density, larger thermal paths to the package surroundings and improved pre-testability.
A typical BGA package 10 is shown in FIG. 1 in an enlarged, cross-sectional view. The package 10 is constructed by first bonding an IC die 12 to a substrate 14 by an adhesive layer 28 and then making electrical connections between the two by wire bonds 16. The IC die 12 is typically interconnected to a plastic resin molded substrate 14 in a transfer molding process. Solder balls 20 are then attached to the backside 18 of the substrate 14 in a post-molding operation. A plastic molding compound or encapsulant 24 is utilized in the transfer molding process to encapsulate the IC die 12 and the bonding wires 16 with a top surface 22 of the substrate. Inside the substrates 14 and 18, is a double-sided printed wiring board (PWB) 30 which has copper laminated to both sides of an insulating plastic material. Via holes 26 are drilled and filled with a conductive metal, i.e., electroless copper, followed by a platform plating process. In more sophisticated BGA package structures, multi-layer substrates which have broader power planes or ground planes, or both are utilized for low inductance and larger thermal-path connections.
Solder balls 20 may be formed on the bottom side 18 of the double-sided PWB 30 by a variety of techniques which include solder-ball attachment and solder-paste screen printing. After the solder balls are formed, a reflow operation usually follows to complete the metallurgical connections.
The BGA package 10 shown in FIG. 1 is formed by a conventional chip scale package technique utilizing wire bonding and plastic encapsulation. The IC chip is mounted in a face-up position with the aluminum bonding pads 32 facing upwardly. In such a position, not only the bonding wires 16 leading from the aluminum bonding pads 32 to the upper copper lead 34 in the PWB 30 need to be excessively long, but also the problem of wire sweep may occur during the plastic molding process. The wire sweep problem causes wire breakage or otherwise defective wire bonds.
In a more recently developed BGA package 40, also known as a micro-BGA package shown in FIG. 2, an IC chip 42 is first bonded to a tape 44 which contains the elastomer 56. After the inner lead bonding process where gold lead 46 is bonded to the IC chip pad 48, solder balls 52 are formed on the TAB tape 44 for making connections with the lead fingers 46 and subsequently with the IC chip 42. The handling of the flexible TAB tape 44 and the lead fingers 46 is problematic and frequently cause processing difficulties. In the final stage of the process, a liquid epoxy molding compound 54 is sequentially injected into a mold in which the chip 42 and the tape 44 are positioned to encapsulate the package 40. In the micro-BGA structure 40, the fabrication process is complicated since the alignment between the IC chip 42, the lead fingers 46 and the TAB tape 44 must be precisely controlled, the packaging process can only be carried out at a high cost.
It is therefore desirable to form a chip scale package by a wire bonding method, instead of a inner lead bonding method. The wire bonding technique is well established and the tooling for carrying out such bonding process is readily available. However, as shown by the conventional wire bonded structure of FIG. 1, the length of the wire bond is long which requires a long fabrication time. Furthermore, a wire sweep problem during encapsulation can be caused by the long bonding wires.
It is therefore an object of the present invention to provide a method for forming chip scale packages that does not have the drawbacks or shortcomings of the conventional wire bonding method for forming such packages.
It is another object of the present invention to provide a method for forming chip scale packages that utilizes an established method of wire bonding and readily available wire bonding tools.
It is a further object of the present invention to provide a method for forming chip scale packages that uses shortened bonding wires such that the process time can be reduced.
It is another further object of the present invention to provide a method for forming chip scale packages by utilizing a wire bonding technique with shortened bonding wires such that the wire sweep problem during a plastic encapsulation process can be alleviated.
It is still another object of the present invention to provide a method for forming chip scale packages by utilizing a wire bonding method in which an IC chip is bonded in a face-down position to interconnections on an insulating substrate.
It is yet another object of the present invention to provide a method for forming chip scale packages by utilizing a wire bonding technique in which an insulating substrate having a recessed peripheral area equipped with interconnections is used.
It is still another further object of the present invention to provide a method for forming chip scale packages by a wire bonding technique by first bonding an active surface of an IC chip to an interposer by adhesive means.
It is yet another further object of the present invention to provide a chip scale package that includes an IC chip which is bonded in a face-down position to an interposer, an interposer that is equipped with a recessed peripheral region and shortened bonding wires required for bonding the IC chip to the interposer.